The present invention is generally directed to integrated circuits and a process for the formation thereof. More specifically, present invention is directed to the improved performance, reliability, and yield of semiconductor and other related devices by providing material layers having desired functionalities (DF), desired performance (DP), and built in reliability (BIR).
The invention of the transistor in 1948 followed by the invention of integrated circuits in 1957 has led to the development of modern microelectronics, which is globally considered as the driver of economic growth. The heart of the modem microelectronics are the silicon integrated circuits or popularly known as silicon chips. Lower cost, high speed, smaller size, and improved reliability of each generation of silicon chips are responsible for the sustained economic growth in the last three decades.
A global examination of the advanced electronic, optical, mechanical, chemical and biological products show that the advances in the field of silicon chip technology have benefited directly or indirectly the manufacturing of other products. As an example of the direct benefit, the success of silicon chip led to the development of the field of solid free form fabrication (SFF) and rapid prototyping (RP). Some details of SFF and RP are described in Chapter 4, xe2x80x9cSolid free form fabrication (SFF) and rapid prototypingxe2x80x9d of the book, xe2x80x9c21st Century Manufacturingxe2x80x9d pp. 130-170, 2000 by P. K. Wright, which is also incorporated herein by reference. Another example of the direct benefits of silicon chip technology is the development of DNA chips and micro-arrays. Some details of DNA chips and micro-arrays are described in an article and titled xe2x80x9cDNA Micro-array (genome Chips)xe2x80x9d, by L. Shi, httD://www.gene-chips.com, which is also incorporated herein by reference. Indirectly, the development of improved controllers, high performance robots, information systems as well as improved precision has helped every manufacturing industry. As a specific example of indirect benefits, more and more things that used to be controlled by mechanical or electro-mechanical systems in a closed loop are driven now by silicon chip based microprocessors.
Currently, most advanced silicon chips are using circuits with feature size of 180 nm. At the cost of several billion dollars, the silicon IC industry is currently in the process of switching from 200 mm diameter wafers to 300 mm diameter wafers. Many experts are predicting that in near future, further shrinking of silicon ICs is coming to end. Some of these issues are discussed in an article titled, xe2x80x9cThe End of the Road for Siliconxe2x80x9d, M. Schultz, Nature, vol. 99, pp. 729-730, 1999, which is also incorporated herein by reference.
In order to keep the success of silicon IC industry moving in the 21st century, the introduction of new materials, further reduction of the parasitic resistance and capacitance, use of higher aspect ratios of vias and trenches is a necessity. The conventional methods of deposition such as physical vapor deposition have several disadvantages in terms of step coverage, control of stoichiometry of the films and the possibility of selective deposition. Conventional chemical vapor deposition (CVD) techniques also are not suitable for the fabrication of future silicon ICs. As an example, one of the most serious problems concerned with conventional CVD of low resistivity metal films used in the sub-100 nm silicon IC fabrication is the rough surface morphology due to the presence of the large crystal grains. Some of these issues are discussed in an article titled, xe2x80x9cReaction and Film Properties of Selective Properties of Selective Titanium Silicide Low-Pressure Chemical Vapor Depositionxe2x80x9d, K. Saito and co-workers, Journal of Electrochemical Society, vol. 141, pp. 1879-1885, 1984, which is also accompanied by reference. Though plasma enhanced CVD has improved surface morphology, the main disadvantage comes in terms of the damage caused to the surface and substrate. Thus, there is a need to invent a CVD technique, which overcomes all of, previously mentioned drawbacks and offers a very low contact resistance.
The manufacturing of sub-70 nm CMOS ICs will also require invention of processing techniques that can provide very high quality junctions. Techniques such as molecular beam epitaxy, and excimer laser annealing for junction formation are being investigated. However, these techniques suffer from severe drawbacks in terms of throughput and defects. Conventionally substrate heating is used during laser crystallization to increase the melt duration and therefore decrease the nucleation rate. This leads to longer processing cycle times and increased manufacturing complexity apart from causing lateral temperature gradients leading to high thermal stress. Also the very high energy density excimer lasers used during the processing beyond the lateral growth regime leads to the roughness at the interface. Small geometry devices are more susceptible to interface roughening as a result of much faster cooling. The use of high energy density lasers also causes blisters on surface. This would not only result in high surface damage, but also degrade device parameters like minority carrier lifetime due to microscopic defects created during the process.
The challenge faced by silicon IC industry is to invent processes land equipment that are capable of providing devices with feature size as small as 1-10 nm using substrates of the diameter in the range of 300 mm and higher. From system point of view, future systems on Chip will have diverse functions (e.g. computing, sensing, imaging, servo mechanics, memory etc.) all integrated on a single chip. These complex systems on chip will be low-cost, ultra small and highly reliable. In order to meet future challenges of silicon IC chips and other related products, the layers of materials grown, deposited or processed on different substrates will have horizontal and or vertical dimensions as small as 1 nm. These different layers of materials either patterned by lithography or written directly will be used in the development of chips having components of the order of millions to billions with diverse functionalities. Due to the chip complexity, testing of such chips may be more expansive than the manufacturing cost. Some of these issues for developing future systems on chip are described in an article and titled, xe2x80x9cCurrent reliability issues and future technologies for systems on silicon-process, circuits, chip architecture, and designxe2x80x9d, Takeda et al, Microelectronics and Reliability, Vol. 40, pp. 897-908, 2000, which is also incorporated herein by reference.
In future, a single layer of material will have to perform more than one function. As an example, the gate material used in the fabrication of metal-insulator field effect transistor (MISFET) will have to provide appropriate work function as well as a barrier against the transportation of any type of defects or flaws (microscopic as well as macroscopic) into the gate dielectric material.
In the fabrication of micro-electromechanical systems (MEMS), stiction and wear are two major problems. Some of these issues of MEMS are described an article and titled, xe2x80x9cEffect of W Coating on Microengine Performancexe2x80x9d, Mami et al., Proc. 2000 IEEE international reliability Physics Symposium Proc. pp. 146-151, 2000, which is also incorporated herein by reference. The reduction of micro-roughness at each surface and interface as well as reduction of stress can improve the performance and reliability of all MEMS products.
Devices based on magnetic materials such as hard disk storage, magnetic static random access memory (MRAM) etc. also need defect free, and stoichiometric films. Some of the materials used in the magnetic devices are usually a few nanometer thick, as described in an article, xe2x80x9cRead-Write Heads,xe2x80x9d J. Baliga, Semiconductor International, vol. 23 (10), pp. 95-102, 2000, which is also incorporated herein by reference.
Thermal processing is an integral part in the formation of different layers used in the fabrication of electronic, magnetic, optical and super conducting devices. As compared to thermal energy, the photochemical and photo physical effects associated with the use of photons (with wavelength less than about 800 nm) have the advantage of using excited states. Some details of thermal and photochemical reactions are described in Chapter 1, xe2x80x9cBasic Principles of Photochemistryxe2x80x9d of the book, Principles and Applications of Photochemistry, pp. 1-5, 1988 written by R. P. Wayne, which is also incorporated herein by reference.
The use of electronic excited states in the formation of material can lead to the reduction of processing time, reduction of processing temperature, reduction of microscopic defects and thermal stress. In the case of removal of material, the use of electronic excited state is very important in the residual removal by providing volatile products. This concept is very important for etching new materials (e.g. IrO2, PbLaZrTiO3 etc.) that are supposed to be important in the fabrication of sub-100 nm feature size circuits. Some details of electronic excited states are described in Chapter 6, xe2x80x9cPhotochemical Reaction Modelsxe2x80x9d of the book, xe2x80x9cExcited States and Photochemistry of Organic Molecules,xe2x80x9d pp. 309-320, 1995 by M. Kiessinger and J. Michl, which is also incorporated herein by reference.
Therefore, a need currently exists for a way to form and remove layers of material having desired functionalities (DF) with desired performance (DP) and built in reliability (BIR) on silicon and other substrates for manufacturing advanced electronic, optical, mechanical, chemical, and biological products, as well as low-cost complex Systems-on Chip (SOC).
The present invention recognizes and addresses the forgoing disadvantages, and others of prior art constructions, techniques and methods.
Accordingly, it is an object of the present invention to provide a process for forming a layer of material having desired functionalities (DFs) with desired performance (DP) and built in reliability (BIR) on silicon and other substrates.
Another object of the present invention is to provide a process for forming or removing a layer of material with microscopic homogeneity on silicon and other substrates using infinitesimal sources of materials in gaseous, liquid or solid form, infinitesimal thermal and a-thermal sources of energy.
Another object of the present invention is to choose chemical reaction paths in the formation of a material.
Another object of the present invention is to provide process for forming a layer of material with thickness ranging from a single monolayer to several microns.
Another object of the present invention is to provide the in-situ processing (e.g. in-situ cleaning of the surface of the substrate, restoration of crystalline surface material with minimum surface defects, in-situ formation and or in-situ deposition and in-situ annealing) capabilities of layer formation.
It is another object of the present invention to provide a process for forming a layer of material with minimum microscopic and macroscopic defects on a substrate useful in the formation of integrated circuits.
The inventive apparatus comprises a processing chamber in which is disposed a silicon or other related substrate or work piece. The substrate can be in vertical or horizontal arrangement within the chamber. The chamber provides material supplies (solid, liquid, and gases), as well as thermal and a-thermal energy sources. The thermal energy is preferably supplied to the substrate from the backside of the wafer (i.e., the side where no deposition, formation or processing takes place). The a-thermal energy, as well as the layer forming materials, can be supplied to the substrate from either front and/or backside of the substrate.
The substrate can be rotated at a predetermined speed. A ring provided outside the substrate supplies the liquid and/or gaseous materials used in the formation of the layer. The ring structure provides the flexibility of introducing complex reactants, as well as reactant heating and/or cooling environments separately without making changes to the existing chamber and the systems. Such an arrangement substantially isolates the chamber walls, and a local cleaning of the ring structure can also be performed.
If the reactants are changed such that the partial pressure and/or the reactant concentration are altered, the ring structure can be easily replaced and a new ring sub-system can be introduced. In essence, the ring structure permits the accurate, timely, and well-monitored delivery of a multitude of gaseous, liquid, and solid precursors. Further, the ring system conditions the reactants to enter the environment in the vicinity of the substrate such that a mono-layer for integrated circuits with sub-100 nm feature sizes are formed with repeatability and controllability, thereby increasing device reliability.
The primary processing criteria is also important. The inventive system is automated to fulfill the factory automation requirements. The costs of ownership improvements are important embodiment of this invention. The throughput and footprint improvements that are, substantially different than prior art are disclosed here to provide the cost of ownership advantages to the user.
The inventive chambers are flexible, thereby facilitating lateral, as well as vertical expansion of the system. In the case of lateral expansion, multiple substrates are processed in the same chamber. The substrates are introduced such that the reaction environment throughout the chamber is substantially the same.
As a specific example, if the metal films (for application in interconnect system of an integrated circuit) are to be deposited at a temperature of 400xc2x0 C., we propose to introduce one, two, three or four substrates simultaneously and the thermal and the reactant delivery components of the system is optimized such that all substrates heat to similar temperatures uniformly, independent of the thermal mass, and reactants distribute themselves such that the concentration of the species is uniform across all substrates. Such uniform heating is accomplished via multiple thermal sources and the reactant uniformity is optimized to provide concentration of the reactant species.
The above described system can be used not only to process integrated circuits, but can also be used to process other devices such as, but not limited to lasers, light emitting diodes, and modulators.